Presently an analog test standard (IEEE P1149.4) is in development to provide the electronics industry with analog test circuitry at input and output pins of analog and mixed signal integrated circuits. The test circuitry is intended to allow scan access of analog pins for the purpose of: (1) providing a means of verifying pin to pin interconnect, and (2) to provide a means for measuring elements found within the pin to pin interconnect, such as resistors, inductors, capacitors, diodes, transistors, or combinations of these elements forming more complex pin to pin networks. Prior art relating to the P1149.4 standard is depicted in a paper published at the 1993 International Test Conference entitled "Structure and Metrology For an Analog Testability Bus" by Parker.
FIG. 1 illustrates the prior art analog cells placed at the output pin 101 of IC1 and at the input pin 103 of IC2. The output pin of IC1 is connected to the input pin of IC2 via an interconnect comprising a series resistor R1. The input and output analog cells comprise scan operated switches 105, 107, 109 and 111 for closing the pin interconnect to Vmax (+15), Vmin (ground (G)), analog bus 1 (AB1) pin, and analog bus 2 (AB2) pin, respectively. In addition, the cells comprise a core disconnect (CD) capability for isolating the IC1 and IC2 core logic from the pin interconnect during testing, and a digital receiver (DR) which allows digitization of analog signals passed between IC1 and IC2 pins during test. The DR operates to receive the pin voltage, compare the voltage to a voltage threshold (Vt), and output a logic one ff the pin voltage is greater than Vt, or a logic zero if the pin voltage is less than Vt. The value of Vt is internally fixed inside each IC at approximately the midpoint voltage between Vmax and Vmin, say 1/2(Vmax-Vmin). These prior art analog cells and their operation are described in detail in the Parker paper.
The test cells can be made to operate in two test modes, digital test mode and analog test mode. During digital test mode, the Vmax and Vmin cell switches 105 and 107 are operated to transmit logic levels (in this case +15 and G voltage swings) from IC pin 101, through the resistive interconnect R1, to be received and digitized to a logic 1 or 0 by the DR at the IC pin 103. Thus the digital test mode uses the Vmax, Vmin, and DR portions of the cells. The digital test mode is modelled after the operation of an existing standard for boundary scan testing, IEEE 1149.1. During analog test mode, the AB1 and AB2 switches 109 and 111 are operated to connect the resistive interconnect to an external test resource. For example the AB1 pin of IC1 could connect IC1's pin 101 to an external signal source and the AB2 pin of IC2 could connect IC2's pin 103 to an external signal monitor. In this arrangement, the external signal source at AB1 can input a signal to the pin of IC1, pass the signal through the resistive interconnect between IC1 and IC2 to be output to the external signal monitor via the AB2 pin of IC2.
The analog test mode can also measure the value of R1 using guarding techniques. The guarding technique uses either the Vmin or Vmax switch 105 or 107 in combination with the AB1 and AB2 switches 109 and 111. During guarding, the Vmin or Vmax switch 105 or 107 is closed to place a known voltage reference on the pin 103 of IC2. With a known voltage reference, say Vmin (G), placed on the IC2 pin 103, a known current can be injected at IC1's AB1 pin to flow from IC1's interconnect pin 101, through R1, and into the pin 103 of IC2. The voltage drop across R1 can then be determined by taking voltage readings at the IC2 pin 103 (using AB2), then at the IC1 pin (again using AB2), then dividing the voltage difference by the known current injected at AB1 of IC1. The external test resource provides a high input impedance at the AB2 pins, so almost zero current flows between the test resource and the AB2 pins. With almost zero current flow, the voltage drop across the AB2 switches 111 is approximately zero, resulting in the voltage reading at the AB2 pins being approximately equal to the voltage present across R1 at the pins 101 and 103 of IC1 and IC2. Guarding measurement techniques are well know by those skilled in the art of testing. The way guarding is utilized in the prior art test cell of FIG. 1 for more complex interconnect networks is explained in detail in the Parker paper, but the basic guarding concept has been described here.
In FIG. 1, it is seen that a short which electrically bypasses R1 could occur during assembly of the circuit. The digital test mode can't detect the short since the test is based on the transfer of logic levels. However, the analog test mode, using the measurement technique, can. Thus, while the digital test mode is the fastest test method to verify an interconnect, the analog test mode is the only one that can analyze the network to prove the resistor is in the interconnect and is correct in value. The following problems are identified with respect to the prior art test cell.
One problem with the arrangement of switches in the prior art test cell, as identified in the present work, is illustrated in FIG. 2. The problem arises because not all interconnected ICs will have the same supply voltages. In the FIG. 2, IC1 is supplied by +15 and -15 volt supplies, while IC2 is supplied by +5 and -5 volt supplies. R1 in the interconnect serves as a current limiter so that unexpectedly high voltage levels from IC1 cannot damage IC2. During normal (not test) operation, the core logic of IC1 is designed to output electrically safe voltage levels to IC2. However, during test mode (both analog and digital test modes) the core logic is isolated (by the CD) from the pin 101 of IC1 and the Vmax and Vmin switches 105 and 107 are operated to generate the voltages output to IC2. In FIG. 2 it is seen that in test mode, Vmax and Vmin switches 105 and 107 cause +15 and -15 volt swings to be output from IC1 at 101. If R1 is in the path, IC2 will probably not be damaged by these voltage output swings since R1 serves to limit the current flow into IC2. However if a short occurs that electrically bypasses R1, IC2 could be subjected to the full +15 and -15 volt swings outputs from IC1 and the resulting high current flows.
The protection diodes at IC pins are designed to clamp input voltages from exceeding the IC's supply voltages. The upper protection diode D1 of IC2 clamps the input pin voltage so that it never becomes more positive than the +5 volt supply plus the diode voltage drop, approximately +5.06 volts. The bottom protection diode D2 of IC2 clamps the input pin voltage so that it never becomes more negative than the -5 volt supply plus the diode voltage drop, approximately -5.06 volts. Protection diodes such as D1 and D2 are designed to protect ICs from transient voltage spikes that may occur in system operation. They are not designed to clamp sustained large voltage levels for long periods of time.
In the event that the short exists across R1 (as shown by dotted lines), the upper protection diode D1 at the pin 103 of IC2 is driven hard into forward bias by the 10 volt difference between the +15 volt supply of IC1 and the +5 volt supply of IC2. For example, when IC1 outputs +15 volts via the Vmax switch 105, a large current flows from IC1's +15 volt supply, out of the IC1 pin 101, through the short across R1 to the pin 103 of IC2, through the upper forward biased protection diode D1 of the IC2 pin 103, and to the +5 volt supply of IC2. Also, when -15 volts is output from IC1, the bottom protection diode D2 at the pin 103 of IC2 is driven hard into forward bias by the 10 volt difference between the -5 volt supply of IC2 and the -15 volt supply of IC1. Again, when IC1 outputs -15 volts via the Vmin switch 107, a large current flows from IC2's -5 volt supply, through the bottom forward biased protection diode D2 of IC2, out of the IC2 pin 103, through the short across R1 to the pin 101 of IC1, and to the -15 volt supply of IC1. The results of these large, sustained current flows through the short during test mode can result in the destruction of the protection diodes or even IC2. Although FIG. 2 shows one example of the problem with ICs having unbalanced supply voltages, it should be understood that large test voltages output from IC1 could be connected to other devices (power transistors, SCRs, motor controllers, etc) that also may be damaged or cause damage in other devices.
The size of analog test cells and the load they place on input and output pin signals is a concern to mixed signal and analog IC designers. One example test cell that has been discussed within the P1149.4 standard working group is shown in FIG. 11. This cell is similar to the prior art cell of FIG. 1, with the exception that the Vmax switch 105 is removed for the purpose of reducing the cell's size and to eliminate one switch load from being connected to the signal line 1101 during normal (non-test) operation. The cell of FIG. 11 allows the AB1 or AB2 switch 109 or 111 to function in place of the removed Vmax switch 105 during digital test mode. For example, during digital test mode an external voltage can be input on the AB1 or AB2 pin and the respective AB1 or AB2 switch 109 or 111 operated to provide the voltage output previously provided by the Vmax switch 105 of the cell in FIG. 1.
While the test cell of FIG. 11 does achieve a reduced size and load test cell, it does not address the problems identified. For example, while the cell allows the high voltage level of the voltage swing during digital testing to be supplied from an AB pin and switch, the low voltage level of the voltage swing is still supplied by the internal Vmin switch 107. Thus when IC1 and IC2 are supplied by unmatched supply voltages, as shown in FIG. 11, the bottom diode D2 of IC2 is still subjected to damaging high current flows as previously described.
Another problem with the prior art test cell, as identified in the present work, involves how the voltage threshold (Vt) for the DR is developed. As previously described, the DR receives voltage input from the IC pin and converts it into logic levels that can be scanned out for inspection by comparing the pin voltage to Vt. If the pin voltage is above Vt, a logic one is produced by the DR. If the pin voltage is below Vt, a logic zero is produced by the DR. The prior art cell establishes the value of Vt internal to the IC and places it at around 1/2 the voltage difference between the IC's Vmax and Vmin voltages.
The problem with establishing a fixed Vt internal to the IC is that it cannot be universally used to determine whether a voltage at a pin is a logic one or a logic zero. FIG. 3 illustrates IC1 connected to IC2 via a resistive network comprising resistors R1, R2 and R3. In this example, R2=R3, and R1=2.times.R2. The resistors form a voltage divider network between IC1 and IC2, causing the voltage level input to the receiving IC to be 1/3 the voltage level output from the transmitting IC, i.e. IC2 voltage input=IC1 voltage output times R3/(RI+R3), or, in the opposite direction, IC1 voltage input=IC2 voltage output times R2/(RI+R2). In digital test mode, if IC1 outputs +15 volt (Vmax) and G (Vmin) voltage swings to IC2, IC2 will receive +5 volt and G swings at its pin 103 due to the voltage division by R1 and R3. Since the Vt of IC2 is fixed close to the mid-point between its Vmax and Vmin supplies (say 7.5 volts), its DR interprets both the +5 volt and G inputs as being a logic zero. Thus, in the example arrangement of FIG. 3, the digital test mode of the prior art cell is not able to pass a recognizable logic one from IC1 to IC2 due to the voltage divider in the pin to pin interconnect.
While the example in FIG. 3 shows an interconnect that prevents logic ones from being output from IC1 and recognized at IC2, it should be clear that other examples could show how logic zeros could be prevented from being output from IC1 and recognized at IC2. For example in FIG. 4, simply connecting R2 and R3 to +15 volts instead of G and leaving all other connections the same as in FIG. 3 illustrates an interconnect where a logic zero from IC1 is not recognizable by IC2. In digital test mode, IC1 outputs +15 volt logic one and G logic zero voltage swings to IC2. However due to the voltage divider of R1 and R3, IC2 only receives +15 volt and +10 volt (15 V.times.2/3) swings at its pin 103. Since the Vt of IC2 is fixed at approximately 7.5 volts, its DR interprets both the +15 and +10 volt inputs as being a logic one. Thus, in the example arrangement of FIG. 4, the digital test mode of the prior art cell is not able to pass a recognizable logic zero from IC1 to IC2 due to the voltage divider in the pin to pin interconnect.
To overcome the above-described problems, a need has arisen for a new analog test cell. A new analog test cell architecture according to the present invention eliminates the Vmax and Vmin switches of the prior art cells which provided connection of the IC's pin to the supply voltage rails of the IC. The new cell architecture eliminates the internally produced Vt for the DR which determined the reference voltage for recognizing logic one and zero voltage levels at the IC's pin. The new cell adds a guard switch which allows connecting the IC pin to an externally supplied reference voltage. The external reference voltage for the cell's guard switch is provided by the addition of an IC pin referred to as a reference pin. The new cell also connects the reference pin up to the DR to provide an externally supplied and regulated Vt level for use during the digital test mode.